1. Field of the Invention
The present invention relates generally to semiconductor memory devices having hierarchical row selecting lines and, more particularly, to a semiconductor memory device operative with an improved access time, decreased power consumption and enhanced reliability by providing hierarchical row selecting lines and word lines therein.
2. Description of the Background Art
FIG. 8 is a block diagram showing a first example of a conventional semiconductor memory device. Referring to the figure, row address data is externally applied to a row address input terminal group 1 to be amplified or inverted by a row address buffer 2, and then applied to a row address decoder 3. The row address decoder 3 decodes the row address data applied via input terminal group 1.
Column address data is externally applied to a column address input terminal group 4 to be amplified or inverted by a column address buffer 5, and then applied to a column address decoder 6. The column decoder 6 decodes the column address data applied via input terminal group 4. A memory cell array 7 is formed of a plurality of memory cells arranged in matrix for storing information. A read voltage having a small amplitude read from memory cell array 7 is supplied via a multiplexer 8 to a sense amplifier 9 to be amplified. An output of sense amplifier 9 is further amplified by an output data buffer 10 to a required level that the output is extracted to the outside of the semiconductor memory device, and is then externally outputted via a read data output terminal 11.
Write data is applied to a write data input terminal 12 to be amplified by an input data buffer 13. Further, a terminal 14 is supplied with a chip select input signal, while a terminal 15 is supplied with a read/write control signal. A read/write control circuit 16 controls sense amplifier 9, output data buffer 10 and input data buffer 13 in accordance with chip selection/non-selection and data read/write mode which are determined by those signals.
FIG. 9 is a diagram showing the configuration of peripheries of memory cell array 7 in the semiconductor memory device shown in FIG. 8. FIG. 9 shows, for simplification, a double-row double-column configuration of memory cell array 7. Referring to FIG. 9, memory cells 24a-24d are provided at respective intersections of bit line pairs 20a, 20b and 21a, 21b and word lines 22 and 23 connected to an output end of row decoder 3. In addition, a plurality of bit line loads 25a, 25b, 26a and 26b are provided having their respective one ends connected to a power source 18 and the other ends connected to their corresponding bit lines.
Further, transfer gates 27a, 27b, 28a and 28b constituting multiplexer 8 shown in FIG. 8 are provided each having its gate supplied with an output signal of column decoder 6 shown in FIG. 8, its drain or source connected to its corresponding bit line and its source or drain connected to a corresponding one of input/output lines (hereinafter referred to as I/O lines) 29a and 29b in a pair. A potential difference between I/O lines 29a and 29b is detected by sense amplifier 9, and an output thereof is amplified by output buffer 10.
For each memory cell 24 in FIG. 9, for example, a high resistance load-type MOS memory cell shown in FIG. 10A or a CMOS-type memory cell shown in FIG. 10B is employed.
The memory cell shown in FIG. 10A comprises driver transistors 41a and 41b. The transistor 41a has its drain connected to a storage node 45a, its gate connected to a storage node 45b and its source grounded. The transistor 41b has its drain connected to storage node 45b, its gate connected to storage node 45a and its source grounded. The memory cell 24 further comprises access transistors 42a and 42b. The transistor 42a has its drain or source connected to storage node 45a, its gate connected to word line 22 or 23 and its source or drain connected to bit line 20a or 21a. The transistor 42b has its drain or source connected to storage node 45b, its gate connected to word line 22 or 23 and its source or drain connected to bit line 20b or 21b. The memory cell 24 further comprises load resistors 43a and 43b having their respective one ends connected to power source 18 and the other ends connected to respective storage nodes 45a and 45b.
The memory cell 24 shown in FIG. 10B comprises p channel transistors 44a and 44b in place of load resistors 43a and 43b of memory cell 24 shown in FIG. 10A. The transistor 44a has its drain connected to storage node 45a, its gate connected to storage node 45b and its source connected to power source 18. The transistor 44b has its drain connected to storage node 45b, its gate connected to storage node 45a and its source connected to power source 18.
An operation of the conventional semiconductor memory device shown in FIGS. 8 to 10B will now be described. Such case is considered that memory cell 24a in memory cell array 7 is selected. In this case, a row address signal corresponding to a row, to which memory cell 24a to be selected is coupled, is inputted from row address input terminal group 1, so that word line 22 to which memory cell 24a is connected attains a selection level (e.g., logical high or the H level) and the other word line 23 attains a non-selection level (e.g., logical low or the L level).
Meanwhile, a column address signal for selecting a column corresponding to bit line pair 20a, 20b, to which memory cell 24a to be selected is connected, is inputted from column address input terminal group 4, so that only transfer gates 27a and 27b connected to that bit line pair 20a, 20b are rendered conductive. Consequently, only the selected bit lines 20a and 20b are connected to a pair of I/O lines 29a and 29b, respectively. The other bit lines 21a and 21b become a non-selection state and then separated from I/O line pair 29a, 29b.
A read operation of selected memory cell 24a will now be described with reference to a timing chart of FIG. 15. It is now assumed that storage node 45a of memory cell 24a is at the H level and storage node 45b is at the L level. At this time, one driver transistor 41a in the memory cell is nonconductive, while the other driver transistor 41b is conductive. Access transistors 42a and 42b of memory cell 24a are both conductive since word line 22 is in the selection state at the H level. Accordingly, a direct current flows through such a path as power source 18.fwdarw.bit line load 25b.fwdarw.bit line 20b.fwdarw.access transistor 42b.fwdarw.driver transistor 41b.fwdarw.ground.
However, a direct current does not flow through the other path, power source 18.fwdarw.bit line load 25a.fwdarw.bit line 20a.fwdarw.access transistor 42a.fwdarw.driver transistor 41a.fwdarw.ground because driver transistor 41a is non-conductive. At this time, a potential on bit line 20a, through which the direct current does not flow, attains a value obtained by (supply potential -Vth) where a threshold voltage of bit line load transistors 25a, 25b, 26a and 26b is Vth.
Meanwhile, a potential on bit line 20b, through which the direct current flows, becomes a value obtained by (power supply potential -Vth -.DELTA.V) since the potential is divided by conductive resistances of driver transistor 41b, access transistor 42b and bit line load 25b and consequently decrease by .DELTA.V from (power supply potential-Vth). Here, .DELTA.V is called a bit line amplitude, which is normally about 50-500 mV and is controlled depending on the magnitude of the bit line load.
This bit line amplitude appears on I/O lines 29a and 29b via conductive transfer gates 27a and 27b to be amplified by sense amplifier 9. After further amplified in output buffer 10, the output of sense amplifier 9 is read out of output terminal 11 as a data output. In reading, input data buffer 13 is controlled by read/write control circuit 16 so as not to drive I/O line pairs 29a, 29b.
In writing, data is written in the memory cell by forcedly lowering the potential on the bit line, in which data of the L level is to be written, down to a lower potential and raising the potential on the other bit line up to a higher potential. For writing inverted data in memory cell 24a, for example, data input buffer 13 causes I/O line 29a to attain the L level and the other I/O line 29b to attain the H level. Accordingly, bit line 20a attains the L level and the other bit line 20b attains the H level, so that the data is written in memory cell 24a.
FIG. 11 is an electrical circuit diagram showing a sense amplifier and I/O line driving circuit. Referring to the figure, NchMOSFETs 59 and 60 constitute a differential input circuit, having their gates supplied with differential input signals Vin and Vin, respectively. The respective sources of NchMOSFETs 59 and 60 are connected in common to a power-down NchMOSFET 61. The NchMOSFET 61 is rendered conductive in response to a chip enable signal (CE) inputted to an input terminal 62. The NchMOSFETs 59 and 60 have their respective drains connected to respective drains of PchMOSFETs 57 and 58 constituting a current mirror circuit, their respective sources connected to a power source Vcc and their respective gates connected in common. An amplification output is obtained from a connection point between NchMOSFET 60 and PchMSOFET 58.
An I/O line load circuit 50 comprises NchMOSFETs 55 and 56 having their respective sources connected to a pair of I/O line 29a and I/ line 29b to be active loads. The I/O line 29a and I 29b are connected via respective terminals 51 and 52 to the respective sources of selecting MOSFETs 27 and 28 and to memory cell 24 shown in FIG. 9. The respective gates and drains of MOSFETs 55 and 56 are connected in common to a power supply Vcc.
FIG. 12 is a diagram showing one example of the layout of the memory cell shown in FIG. 10A. Referring to FIG. 12, an active region 82 is surrounded by an isolation region 81. A first polysilicon 81 formed of polysilicon or silicide is connected to active region 82 by a shared contact 84. A second polysilicon 85 formed of polysilicon or silicide connects, through shared contact 84, active region 82 and another active region 82 or first polysilicon 83 and another first polysilicon 83. A second polysilicon contact 86 is provided on second polysilicon 85. There further formed a third polysilicon 87 employed as a high resistance load, a contact 88 and an aluminum interconnection 89.
In the figure, the denotation 85a represents a memory cell power source line, and 89a, 82a and 82b represent portions to be ground of the memory cell. A transistor 41a has a drain 82c, a gate 83a and a source 82a. A transistor 41b has a drain 82d, a gate 83b and a source 82b. A transistor 42a has a drain 82g, a gate 83c and a source 82c. A transistor 42b has a drain 82f, a gate 83c and a source 82e. Resistors 43a and 43b shown in FIG. 10A comprise third polysilicon 87a and 87b, respectively. The gate 83c constitutes a word line, and portions 89b and 89c constitute bit lines. As apparently seen from FIG. 12, the width of first polysilicon 83 is a gate length L, and the area of first polysilicon 83 occupies a large portion of a cell area.
FIG. 13 is a cross-sectional view of the memory cell shown in FIG. 12 taken along the lines I--I'. Referring to FIG. 13, an active region 82 is surrounded by an isolation region 81. The reference numeral 83 denotes a first polysilicon formed of polysilicon or silicide; 84 denotes a shared contact for coming in contact with active region 82 or first polysilicon 83 in common; 85 denotes a second polysilicon formed of polysilicon or silicide for connecting active region 82 and another active region 82 or first polysilicon and another first polysilicon through shared contact 84; 86 denotes a second polysilicon contact provided on the second polysilicon; 87 denotes a third polysilicon employed as a high resistance load; 88 denotes a contact; 89 denotes a first layer of aluminum; 99 denotes a second layer of aluminum not shown in FIG. 12; and 92-98 denote insulating films.
FIG. 14 shows a double-row eight-column structure out of the memory cell array shown in FIG. 12. This figure shows, for simplification, only isolation region 81, first polysilicon 83, contact 88 and aluminum 89. The denotation 89a represents aluminum of ground line provided for every four columns, and 89b and 89c represent aluminum of bit lines. In this example, a ground potential of the memory cell is provided through the aluminum provided every four columns and through a band-like diffusion region extending perpendicularly to the aluminum in order to reduce the area of layout.
Since the conventional semiconductor memory device is configured as described above, all the memory cells on the same substrate are activated to let a current flow therein from the power source. Therefore, there has been such a disadvantage especially in the configuration of a large capacity semiconductor memory device that a total power consumption becomes increased.
Furthermore, in the large capacity semiconductor memory device, an increase in length of word lines increases the entire resistance of the word lines formed of polysilicon, molybdenum silicide, tungsten silicide or the like having higher resistance than metal. In addition, an increased number of memory cells connected to the same word line causes an increased capacitive load. Consequently, delay time on the word lines is increased, resulting in another disadvantage that a high speed access cannot be performed.
In order to eliminate these disadvantages, a second conventional example of the semiconductor memory device is proposed as shown in FIG. 16, which is, for example, disclosed in Japanese Patent Laying-Open No. 58-211393 and U.S. Pat. No. 4,542,486. This semiconductor memory device comprises N memory cell groups formed by dividing in a column direction a memory cell array formed of memory cells arranged in matrix, memory cell group selecting lines for each selecting a corresponding one of the N memory cell groups, row decoders for each decoding a row address signal of the memory cell group to be accessed, preceding word lines each connected to an output terminal of the corresponding one of the row decoders, AND function gates for each taking a logical product of a selecting signal on the memory cell group selecting line and an output signal on the preceding word line, and word lines connected to output terminals thereof. The preceding word lines and the latter word lines are arranged in parallel in a row direction. FIG. 16 shows one example of such a semiconductor memory device where the memory cell array is divided into N (3) blocks in the column direction to form N (3) memory cell groups 51a-51c.
Referring to FIG. 16, memory cell group selecting lines 52a-52c select their corresponding memory cell groups 51a-51c. A plurality of preceding word lines 55 are connected to outputs of row decoders 54 and are arranged in parallel in one direction. Furthermore, a plurality of AND function gates 56a-56c are provided having their inputs connected to the preceding word lines 55 and the corresponding memory cell group selecting lines. Word lines 53a-53c are connected to the respective outputs of these gates.
Operation of the second conventional example of this semiconductor memory device will now be described. Referring to FIG. 16, word line 53a in memory cell group 51a, for example, is activated by a switching gate 56a receiving as its inputs a signal on preceding word line 55 as a row selecting line and a signal on memory cell group selecting line 52a running vertically to preceding word line 55. In the device of FIG. 16, the time to select a particular row is determined by a delay time on preceding word line 55 and that on word line 53a.
A capacitance of preceding word line 55 does not include a gate capacitance which is the sum of a gate-drain capacitance, gate-source capacitance and gate-substrate capacitance of access transistors 42a and 42b in each memory cell, and hence the capacitance is considerably smaller than the capacitance of a conventional word line including those capacitances. In addition, word line 53a is so short that a CR delay thereon is negligible. Therefore, the employment of the second conventional example makes it possible to substantially reduce the time to select a particular row compared to the conventional.
Moreover, since preceding word line 55 does not constitute a gate electrode, materials of preceding word line as the row selecting line can be selected independently of a work function, and a variety of low resistance materials can be employed.
Since only the memory cells connected to a single word line 53a in the selected memory cell group are accessed in this second conventional example, an ineffective current flowing into the memory cells from the load transistors of the bit lines can be reduced to the amount of 1/(the number of blocks) compared to the conventional, and thus power consumption can also be reduced at the same time.
In the second conventional example of the semiconductor memory device thus structured, however, a memory cell array need be divided into a large number of blocks for achieving lower power consumption. In a larger capacity semiconductor memory device, as the number of AND function gates 56 connected to a single preceding word line 55 becomes increased, the length of the preceding word line 55 itself becomes increased. Accordingly, there was a disadvantage that the capacitance and resistance of the preceding word line 55 both increase, and thus a delay on preceding word line 55 increases.
Moreover, since the large capacity semiconductor memory device requires a large number of divided blocks of the memory cell array for achieving lower power consumption as described above, the capacitance of preceding word line 55 becomes increased, and thus a MOS transistor of row decoder 54 for driving preceding word line 55 operates in a saturation region over a long period of time. This results in such a problem in reliability that due to a so-called hot electron effect in which an intensity of an electric field is increased in a channel region of a miniaturized MOS transistor to allow electrons to flow into a gate oxide film, thereby raising a threshold value of the transistor, a threshold voltage of the MOS transistor fluctuates in time, leading to a shift in access time of the semiconductor memory device. Therefore, due to the disadvantages pointed out in the above, it has been impossible to divide the memory cell array into multi-block in the large capacity semiconductor memory device.
In addition, there has been another problem in reliability of the large capacity semiconductor memory device such that due to the increased capacitance of preceding word line 55 which results in an increase in charge/discharge currents flowing through preceding word line 55, a migration of aluminum occurs thereby causing a disconnection particularly in case where the preceding word line is formed of aluminum metal.